1 november 2003 idt72v11165, idt72v12165 idt72v13165, idt72v14165 idt72v15165 idt and the idt logo are trademarks of integrated device technology, inc. industrial temperature range ? 2003 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. dsc-6359/3 3.3 volt multimedia fifo 256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16, and 4,096 x 16 features ? ? ? ? ? 256 x 16-bit organization array (idt72v11165) ? ? ? ? ? 512 x 16-bit organization array (idt72v12165) ? ? ? ? ? 1,024 x 16-bit organization array (idt72v13165) ? ? ? ? ? 2,048 x 16-bit organization array (idt72v14165) ? ? ? ? ? 4,096 x 16-bit organization array (idt72v15165) ? ? ? ? ? 15 ns read/write cycle time ? ? ? ? ? 5v input tolerant ? ? ? ? ? independent read and write clocks ? ? ? ? ? empty/full and half-full flag capability ? ? ? ? ? output enable puts output data bus in high-impedance state ? ? ? ? ? available in a 64-lead thin quad flatpack (10x10mm and 14x14mm tqfp) ? ? ? ? ? industrial temperature range (?40 c to +85 c) functional block diagram reset logic flag outputs write control read control fifo array wclk wen d 0 - d 15 data in x16 rs ef hf q 0 - q 15 data out x16 rclk ren 6359 drw01 ff oe description the idt72v11165/72v12165/72v13165/72v14165/72v15165 devices are first-in, first-out (fifo) memories with clocked read and write controls. these fifos have 16-bit input and output ports. the input port is controlled by a free-running clock (wclk), and an input enable pin ( wen ). data is written into the multimedia fifo on every clock when wen is asserted. the output port is controlled by another clock pin (rclk) and another enable pin ( ren ). the read clock (rclk) can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. an output enable pin ( oe ) is provided on the read port for three-state control of the output. these multimedia fifos support three fixed flags: empty flag ( ef ), full flag ( ff ), and half full flag ( hf ).
2 idt72v11165/72v12165/72v13165/72v14165/72v15165 3.3v multimedia fifo 256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16 industrial temperature range pin configurations stqfp (pp64-1, order code: tf) top view pin 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 gnd rclk ren oe rs v cc gnd ef gnd q 1 v cc q 2 q 3 gnd q 4 q 5 v cc q 6 q 7 gnd q 8 q 9 q 10 q 11 gnd q 12 v cc 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 11 d 12 d 13 d 14 d 15 gnd dnc (1) wclk wen v cc ff hf q 15 gnd q 14 q 13 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 6359 drw02 gnd gnd v cc dnc (1) gnd d 0 v cc q 0 dnc (1) dnc (1) dnc (1) pin description symbol name i/o description d0?d15 data inputs i data inputs for an 16-bit bus. ef empty flag o ef indicates whether or not the fifo memory is empty. ff full flag o ff indicates whether or not the fifo memory is full. hf half-full flag o the device is more than half full when hf is low. oe output enable i when oe is low, the data output bus is active. if oe is high, the output data bus will be in a high-impedance state. q0?q15 data outputs o data outputs for an 16-bit bus. rclk read clock i when ren is low, data is read from the fifo on a low-to-high transition of rclk, if the fifo is not empty. ren read enable i when ren is low, data is read from the fifo on every low-to-high transition of rclk. when ren is high, the output register holds the previous data. data will not be read from the fifo if the ef is low. rs reset i when rs is set low, internal read and write pointers are set to the first location of the ram array, ff goes high, and ef goes low. a reset is required before an initial write after power-up. wclk write clock i when wen is low, data is written into the fifo on a low-to-high transition of wclk, if the fifo is not full. wen write enable i when wen is low, data is written into the fifo on every low-to-high transition of wclk. when wen is high, the fifo holds the previous data. data will not be written into the fifo if the ff is low. v cc power i +3.3v power supply pins. gnd ground i ground pins. note: 1. dnc = do not connect.
3 idt72v11165/72v12165/72v13165/72v14165/72v15165 3.3v multimedia fifo 256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16 industrial temperature range recommended dc operating conditions symbol parameter min. typ. max. unit v cc supply voltage industrial 3.0 3.3 3.6 v gnd supply voltage 0 0 0 v v ih input high voltage industrial 2.0 ? 5.5 v v il (1) input low voltage industrial -0.5 ? 0.8 v t a operating temperature -40 ? 85 c industrial note: 1. 1.5v undershoots are allowed for 10ns once per cycle. symbol rating industrial unit v term (2) terminal voltage ?0.5 to +5 v with respect to gnd t stg storage ?55 to +125 c temperature i out dc output current ?50 to +50 ma symbol parameter (1) conditions max. unit c in (2) input v in = 0v 10 pf capacitance c out (1,2) output v out = 0v 10 pf capacitance capacitance (t a = +25 c, f = 1.0mhz) notes: 1. with output deselected, ( oe v ih ). 2. characterized values, not currently tested. idt72v11165 idt72v12165 idt72v13165 idt72v14165 idt72v15165 industrial t clk = 15 ns symbol parameter min. typ. max. unit i li (1) input leakage current (any input) ?1 ? 1 a i lo (2) output leakage current ?10 ? 10 a v oh output logic ?1? voltage, i oh = ?2 ma 2.4 ? ? v v ol output logic ?0? voltage, i ol = 8 ma ? ? 0.4 v i cc1 (3,4,5) active power supply current ? ? 30 ma i cc2 (3,6) standby current ? ? 5 ma dc electrical characteristics (industrial: v cc = 3.3v 0.3v, ta = -40 c to +85 c) notes: 1. measurements with 0.4 v in v cc . 2. oe v ih, 0.4 v out v cc . 3. tested with outputs disabled (i out = 0). 4. rclk and wclk toggle at 20 mhz and data inputs switch at 10 mhz. 5. typical i cc1 = 2.04 + 0.88*f s + 0.02*c l *f s (in ma). these equations are valid under the following conditions: v cc = 3.3v, t a = 25 c, f s = wclk frequency = rclk frequency (in mhz, using ttl levels), data switching at f s /2, c l = capacitive load (in pf). 6. all inputs = v cc - 0.2v or gnd + 0.2v, except rclk and wclk, which toggle at 20 mhz. absolute maximum ratings notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v cc terminal only.
4 idt72v11165/72v12165/72v13165/72v14165/72v15165 3.3v multimedia fifo 256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16 industrial temperature range ac electrical characteristics (industrial: vcc = 3.3v 0.3v, ta = -40c to +85c) industrial idt72v11165 idt72v12165 idt72v13165 idt72v14165 idt72v15165 symbol parameter min. max. unit f s clock cycle frequency ? 66.7 m h z t a data access time 2 10 ns t clk clock cycle time 15 ? ns t clkh clock high time 6 ? ns t clkl clock low time 6 ? ns t ds data set-up time 4 ? ns t dh data hold time 1 ? ns t ens enable set-up time 4 ? ns t enh enable hold time 1 ? ns t rs reset pulse width (2) 15 ? ns t rss reset set-up time 10 ? ns t rsr reset recovery time 10 ? ns t rsf reset to flag and output time ? 15 ns t olz output enable to output in low-z (3) 0?ns t oe output enable to output valid 3 8 ns t ohz output enable to output in high-z (3) 38ns t wff write clock to full flag ? 10 ns t ref read clock to empty flag ? 10 ns t hf clock to half-full flag ? 20 ns t skew1 skew time between read clock & write clock for ff and ef 6?ns input pulse levels gnd to 3.0v input rise/fall times 3ns input timing reference levels 1.5v output reference levels 1.5v output load see figure 1 ac test conditions figure 1. output load * includes jig and scope capacitances. 30pf* 330 ? 3.3v 510 ? d.u.t. 6359 drw03 notes: 1. industrial temperature range product for the 15ns speed grade available. 2. pulse widths less than minimum values are not allowed. 3. values guaranteed by design, not currently tested.
5 idt72v11165/72v12165/72v13165/72v14165/72v15165 3.3v multimedia fifo 256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16 industrial temperature range functional description write/read and flag function to write data into to the fifo, write enable ( wen ) must be low. data presented to the data in lines will be clocked into the fifo on subsequent transitions of the write clock (wclk). after the first write is performed, the empty flag ( ef ) will go high. subsequent writes will continue to fill up the fifo. if one continued to write data into the fifo, and we assumed no read operations were taking place, the half-full flag ( hf ) would toggle to low once the 129th (72v11165), 257th (72v12165), 513th (72v13165), 1,025th (72v14165), and 2,049th (72v15165) word respectively was written into the fifo. when the fifo is full, the full flag ( ff ) will go low, inhibiting further write operations. if no reads are performed after a reset, ff will go low after d writes to the fifo. d = 256 writes for the idt72v11165, 512 for the idt72v12165, 1,024 for the idt72v13165, 2,048 for the idt72v14165 and 4,096 for the idt72v15165, respectively. if the fifo is full, the first read operation will cause ff to go high. subsequent read operations will cause the half-full flag ( hf ) to go high. continuing read operations will cause the fifo to be empty. when the last word has been read from the fifo, the ef will go low inhibiting further read operations. ren is ignored when the fifo is empty. signal descriptions inputs data in (d 0 - d 15 ) data inputs for 16-bit wide data. controls reset ( rs ) reset is accomplished whenever the reset ( rs ) input is taken to a low state. during reset, both internal read and write pointers are set to the first location. a reset is required after power-up before a write operation can take place. the half-full flag ( hf ) to high after t rsf . the full flag ( ff ) will reset to high. the empty flag ( ef ) will reset to low. during reset, the output register is initialized to all zeros and the offset registers are initialized to their default values. write clock (wclk) a write cycle is initiated on the low-to-high transition of the write clock (wclk). data setup and hold times must be met with respect to the low-to-high transition of wclk. the write and read clocks can be asynchronous or coincident. write enable ( wen ) when the wen input is low, data may be loaded into the fifo ram array on the rising edge of every wclk cycle if the device is not full. data is stored in the ram array sequentially and independently of any ongoing read operation. when wen is high, no new data is written in the ram array on each wclk cycle. to prevent data overflow, ff will go low, inhibiting further write operations. upon the completion of a valid read cycle, ff will go high allowing a write to occur. the ff flag is updated on the rising edge of wclk. read clock (rclk) data can be read on the outputs on the low-to-high transition of the read clock (rclk), when output enable ( oe ) is set low. the write and read clocks can be asynchronous or coincident. read enable ( ren ) when read enable is low, data is loaded from the ram array into the output register on the rising edge of every rclk cycle if the device is not empty. when the ren input is high, the output register holds the previous data and no new data is loaded into the output register. the data outputs q 0 -q n maintain the previous data value. every word accessed at q n , including the first word written to an empty fifo, must be requested using ren . when the last word has been read from the fifo, the empty flag ( ef ) will go low, inhibiting further read operations. ren is ignored when the fifo is empty. once a write is performed, ef will go high allowing a read to occur. the ef flag is updated on the rising edge of rclk. output enable ( oe ) when output enable ( oe ) is enabled (low), the parallel output buffers receive data from the output register. when oe is disabled (high), the q output data bus is in a high-impedance state. outputs full flag/input ready ( ff ) when the fifo is full, ff will go low, inhibiting further write operations. when ff is high, the fifo is not full. if no reads are performed after a reset, ff will go low after d writes to the fifo. d = 256 writes for the idt72v11165, 512 for the idt72v12165, 1,024 for the idt72v13165, 2,048 for the idt72v14165 and 4,096 for the idt72v15165. ff is synchronous and updated on the rising edge of wclk. empty flag/output ready ( ef ) when the fifo is empty, ef will go low, inhibiting further read operations. when ef is high, the fifo is not empty. ef is synchronous and updated on the rising edge of rclk. half-full flag ( hf ) after half of the memory is filled, and at the low-to-high transition of the next write cycle, the half-full flag goes low and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. the half-full flag ( hf ) is then reset to high by the low-to-high transition of the read clock (rclk). the hf is asynchronous. data outputs (q0-q15) data outputs for 16-bit wide data.
6 idt72v11165/72v12165/72v13165/72v14165/72v15165 3.3v multimedia fifo 256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16 industrial temperature range figure 2. reset timing (1) rs ren , wen hf q 0 - q 15 oe = 0 oe = 1 6359 drw04 rclk, wclk ff ef idt standard mode (2) (1) t rsf t rsf t rsf t rsf t rsr t rs idt standard mode notes: 1. the clocks (rclk, wclk) can be free-running asynchronously or coincidentally. 2. after reset, the outputs will be low if oe = 0 and high-impedanced if oe = 1. note: 1. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ff will go high after one wclk cycle plus t wff . if the time between the rising edge of rclk and the rising edge of wclk is less than tskew1, then the ff deassertion time may be delayed an extra wclk cycle. figure 3. full flag timing d 0 - d 15 wen rclk ff ren t enh t enh q 0 - q 15 data read next data read data in output register low oe t skew1 data write 6359 drw24 wclk no write 1 2 1 2 t ds no write t wff t wff t wff t a t ens t ens t skew1 t ds t a wd (1) (1)
7 idt72v11165/72v12165/72v13165/72v14165/72v15165 3.3v multimedia fifo 256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16 industrial temperature range note: 1. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that ef will go high after one rclk cycle plus t ref . if the time between the rising edge of wclk and the rising edge of rclk is less than t skew1 . then the ef deassertion may be delayed an extra rclk cycle. figure 5. read cycle timing no operation rclk ren ef t clkl t enh t ref last word t a t olz t oe q 0 - q 15 oe wclk wen 6359 drw26 d 0 - d 15 t ens t ens t enh t ds t dh first word t ohz t clk 12 t ref t skew1 t clkh (1) figure 4. write cycle timing note: 1. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ff will go high after one wclk cycle plus t rff . if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 . then the ff deassertion may be delayed an extra wclk cycle. wclk d 0 - d 15 wen ff rclk ren t ds t wff t wff data in valid no operation (1) t skew1 6359 drw25 t ens t dh t enh 1 2 t clkh t clkl t clk
8 corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-360-1753 san jose, ca 95138 fax: 408-284-2775 email: f ifohelp@idt.com www.idt.com idt xxxxx device type x power xx speed x package x clock cycle time (t clk ) speed in nanoseconds process / temperature range 6359 drw32 industrial (-40 c to +85 c) i tf slim thin plastic quad flatpack (stqfp, pp64-1) 15 l low power 72v11165 72v12165 72v13165 72v14165 72v15165 256 x 16 ? 3.3v multimedia fifo 512 x 16 ? 3.3v multimedia fifo 1,024 x 16 ? 3.3v multimedia fifo 2,048 x 16 ? 3.3v multimedia fifo 4,096 x 16 ? 3.3v multimedia fifo industrial ordering information datasheet document history 11/17/2003 pg. 1.
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